1. Field of the Invention
This invention relates to the field of logic design, and more particularly, to a logic design and method for reducing leakage current in logic circuits using field-effect transistors.
2. Background
Referring to FIG. 1, an SRAM memory array is shown. The memory array 10 includes a plurality of memory cells 12 arranged in (n) rows and (m) columns, a row decoder 14, a plurality of word lines 16(l) through 16(n) corresponding to each of the (n) rows in the array, a column decoder 18, and (m) differential bit line pairs BL and BL corresponding to each of the (m) columns. Each pair of differential bit lines BL and BL includes a precharge circuit 20(l) through 20(m) and a write driver circuit 22(l) through 22(m) respectively. Each write enable circuit 22(l) through 22(m) receives a write enable input signal 26(l) through 26(m) from the column decoder 18 respectively.
During a write operation, the precharge circuits 20 precharge the differential bit lines BL and BL for each of the (m) columns of the memory array 10. The row decoder 14 then selects a row in response to a row select address and the column decoder 18 selects a column in response to a column select address. The output of the column decoder 18 activates the write driver circuit 22 corresponding to the selected column. Consequently, the write driver circuit 22 causes the corresponding differential bit lines BL and BL to move in accordance with the data input signal provided at the data signal input 24 of the corresponding write driver circuit 22. For example in a memory array where the precharge is high, if the data input signal received at the data input 24 is high, the bit line BL discharges low and BL remains at the precharge voltage. If the data input signal is low, the bit line BL remains at the precharge level and BL discharges low. The memory cell 12 at the intersection of the selected row and column then stores the data on the moved differential bit lines BL and BL. When the word line 16 is deactivated signalling the end of the write operation, the memory cell 12 stores the data indefinitely until another access operation of the memory cell 12 occurs. The above example shows how a binary data value is stored in a single memory cell 12 of a selected row. With different embodiments, the column decoder 18 may activate a plurality of write driver circuits 22 in response to a selected address. In response thereto, a plurality of data input signals 24 may be written into the plurality of memory cells 12 along the selected row.
Referring to FIG. 2, a prior art logic diagram of a write driver circuit 22 is shown. The write driver circuit 22 includes a data input 24 for receiving the data input signal, an enable input 26 for receiving the write enable signal, write line pass transistors 30 and 32, and inverters 34, 36, and 38. The enable input 26 is coupled to the gates of transistors 30 and 32. The source of the transistor 30 is coupled to the output of inverter 34 and the drain is coupled to the bit line BL. The input of inverter 34 is coupled receive the data input signal provided at the data input 24. The source of the transistor 32 is coupled to the output of inverter 38 and the drain is coupled to the bit line BL. The input of inverter 38 is coupled to the output of inverter 36 and the input of inverter 36 is coupled to receive the data input signal provided at the data input 24.
The write driver circuit 22 has two states, inactive and write. During the inactive state, the write enable input 26 is low, causing the transistors 30 and 32 to be off. The voltage level of the differential bit lines BL and BL is therefore independent of the value of the data input signal because they are not coupled to the output of inverters 34 and 38 respectively. Conversely, during the write state, the bit lines BL and BL are first precharged. The write enable signal 26 then transitions high causing the transistors 30 and 32 to turn on, coupling the bit line BL to the output of inverter 34 and the bit line BL to the output of inverter 38. If the signal at the data input 24 is high, the output of inverter 34 is low, causing the bit line BL to be pulled low through the inverter 34. On the other hand, bit line BL remains high because the output of inverter 38 remains high when the signal at the data input 24 is high. The complement of the above applies when the data input signal is low.
Recently, complementary metal oxide semiconductor field-effect transistors (CMOS) logic has seen ever increasing use in digital systems. As MOSFET technology has evolved, individual MOSFET's have become steadily smaller, i.e., with narrower features. This has allowed more and more MOSFET's to be integrated together in one integrated circuit (IC), as well as to allow the requisite power supply voltage (VDD) to become smaller. Benefits of the former include reduced size and weight and increased operating frequencies, while benefits of the latter include reduced power consumption. However, operating MOSFET's at today's low power supply voltages has the undesirable effect of lowering MOSFET current which reduces the maximum operating frequency. Hence, in order to minimize reductions in circuit performance, the MOSFET threshold voltages (V.sub.TH) are reduced so as to minimize reductions in the MOSFET current. (Further discussion of the relationship(s) between power supply voltage, threshold voltage, and operating performances for MOSFET's can be found in commonly assigned, copending U.S. patent application Ser. No. 08/292,513, filed Aug. 18, 1994, and entitled "Low Power, High Performance Junction Transistor"; the disclosures of which are hereby incorporated by reference.) However, this in turn has the effect of increasing MOSFET leakage current, i.e., MOSFET current flowing when the device is off.
The Applicant believes that if the write driver circuit of FIG. 2 was constructed with the low powered, low threshold transistors discussed in the above referenced copending application, leakage current in the write line pass transistors 30 and 32 of a write driver circuit 22 would adversely affect the operation of the circuit by inducing a read operation failure due to corruption of the bit line voltage levels.